We want to help make your FPGA design experience better. If you've finished an FPGA design within the last 12 months, we'd like you to fill out our brief survey and tell us about your experience. This information will be provided in aggregated form to suppliers of FPGA silicon, tools, and services to help them better meet your future needs.
  

We ask for some information about you including your e-mail address and design experience. Please see our Privacy Statement if you have any questions as to how this information will be handled. techfocus media will do audits of responses to validate the data we collect. Data found to be from invalid sources will be discarded.
We'd also like permission to contact you via e-mail for possible follow-up questions. Please let us know if we may contact you by checking the appropriate box.
  
Please fill out one survey for each FPGA design project. If you don't know the answers to some of the questions, please leave them in their blank (or default) value.
::DESIGNER::

e-mail address:

How many designs have you personally worked on? FPGA: ASIC:

Highest degree Years design experience:

Company name:

::DESIGN::

For what purpose was this FPGA used?
 control DSP embedded app glue logic switching complex SOC other

In what phase of your project was this FPGA design used?

Approximate production volume (how many systems will be produced using THIS design/device):

Size of design team (number of designers) on this device:

Approximate date project completed (YYYY/MM/DD):

How many (working) calendar weeks to complete?

For each phase of the design, indicate approximately how many weeks your team spent on that phase:

micro-architecture
design

RTL coding/
debug

I/O &
constraint specification

IP
integration

floor-
planning

synthesis

place and
route

final timing
debug

on-board
debug

Which of these phases was the most troublesome?

Fastest clock speed in this design (MHz)?

::VENDOR AND DEVICE::

Why did you not choose a smaller or cheaper device? (check all that apply):
insufficient i/o insufficient logic cells embedded IP unavailable
req'd package unavailable req'd speed unavailable

What speedgrade did you use?

 
Why did you choose this FPGA vendor? (rate each factor)
part capability previous success corporate standard support tools


How satisfied were you with this FPGA vendor? (rate each factor)
part capability     support tools
   

::IP::

This design included IP or reused design blocks from: (check all that apply)
internal FPGA vendor EDA vendor other 3rd party

Does your design include a soft-core embedded processor? Nios Microblaze none

::TOOLS::

What design entry method or language was used on this project? (check all that apply)
VHDL Verilog Schematic C-C++ Matlab other

What EDA vendor is the primary source for any (non-FPGA vendor) design tools purchased?
Aldec Cadence Mentor Graphics Simucad Synopsys Synplicity None

Why did you choose this EDA vendor? (rate each factor)
software capability software reliability support service corporate standard price


How satisfied were you with this EDA vendor? (rate each factor)
software capability software reliability support service price

What primary HDL simulator did you use on this project?
Aldec Active-HDL Cadence NC-VHDL/Verilog Mentor ModelSim Simucad Silos Synopsys VCS
other

Why did you choose this HDL simulator? (rate each factor)
supplied by FPGA vendor corporate standard previous experience
     
performance ease of use reliability


How satisfied were you with this HDL simulator? (rate each factor)

performance ease of use reliability


What primary RTL synthesis product did you use on this project?
Altera:Quartus Native Synthesis Mentor:LeonardoSpectrum Mentor:Precision Synopsys:FPGA Compiler
 Synopsys:FPGA Express Synplicity:Synplify Synplicity:Synplify Pro Xilinx:XST

Why did you choose this RTL synthesis tool? (rate each factor)
supplied by FPGA vendor corporate standard previous experience
     
performance ease of use reliability
     
quality of results analysis capability language support


How satisfied were you with this RTL synthesis tool? (rate each factor)

performance ease of use reliability
     
quality of results analysis capability language support

 
::PROJECT::

How many total FPGA designs are part of this project? How many ASIC designs?

Which other FPGA vendors' devices are in this same project? (Check all that apply)
Actel Altera Lattice Xilinx

Are there plans to later replace the FPGA portions of this project with ASIC? Yes No

Was this FPGA design project successful? Yes No
 


I agree techfocus media may contact me by e-mail with follow-up questions
I'd like to subscribe to a weekly fpga journal update e-mail
I'd like to receive a summary of results of this survey by e-mail

please add any other comments or observations about this FPGA project: